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Design Rule Verification Report
Date
:
2/9/2009
Time
:
11:14:27 AM
Elapsed Time
:
00:00:00
Filename
:
C:\User\Daniel\Protel\RF\DelayLinePhaseShifter\DelayLinePower.PcbDoc
Warnings
:
0
Rule Violations
:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=10mil) (All),(All)
0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=12mil) (All)
0
Hole Size Constraint (Min=15mil) (Max=150mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Broken-Net Constraint ( (All) )
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Total
0