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Design Rule Verification Report

Date : 10/16/2009
Time : 8:38:02 AM
Elapsed Time : 00:00:02
Filename : C:\Users\Daniel\Protel\FSS\PDInterface\PDInt.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=15mil) (Max=200mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silkscreen Over Component Pads (Clearance=0mil) (All),(All) 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=8mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Room I1 (Bounding Region = (2850mil, 2950mil, 5350mil, 5950mil) (InComponentClass('I1')) 0
Room I2 (Bounding Region = (5850mil, 2950mil, 8350mil, 5950mil) (InComponentClass('I2')) 0
Room I3 (Bounding Region = (8850mil, 2950mil, 11350mil, 5950mil) (InComponentClass('I3')) 0
Room I4 (Bounding Region = (11850mil, 2950mil, 14350mil, 5950mil) (InComponentClass('I4')) 0
Total 0