Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s1600e
Project ID (random number) 0f0879cf50c54cab9c074ce8809ab430.796ea917ed0f4882b8a80c88ef699210.12 Target Package: fg320
Registration ID 174495228_175299972_0_270 Target Speed: -4
Date Generated 2021-08-19T12:08:22 Tool Flow CommandLine
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz CPU Speed 3498 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=173
  • AGG_IO=173
  • AGG_SLICE=7419
  • NUM_4_INPUT_LUT=8966
  • NUM_BONDED_DIFFM=67
  • NUM_BONDED_DIFFS=67
  • NUM_BONDED_IBUF=19
  • NUM_BONDED_IOB=20
  • NUM_BUFGMUX=24
  • NUM_CYMUX=2882
  • NUM_IOB_FF=10
  • NUM_LUT_RT=1115
  • NUM_SHIFT=2
  • NUM_SLICEL=7418
  • NUM_SLICEM=1
  • NUM_SLICE_FF=9617
  • NUM_XOR=2599
 		NetStatistics
  • NumNets_Active=13575
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=6812
  • NumNodesOfType_Active_CNTRLPIN=6832
  • NumNodesOfType_Active_DOUBLE=28714
  • NumNodesOfType_Active_DUMMY=21286
  • NumNodesOfType_Active_DUMMYBANK=15
  • NumNodesOfType_Active_DUMMYESC=31
  • NumNodesOfType_Active_GLOBAL=819
  • NumNodesOfType_Active_HFULLHEX=831
  • NumNodesOfType_Active_HLONG=307
  • NumNodesOfType_Active_HUNIHEX=4310
  • NumNodesOfType_Active_INPUT=26556
  • NumNodesOfType_Active_IOBOUTPUT=40
  • NumNodesOfType_Active_OMUX=13464
  • NumNodesOfType_Active_OUTPUT=13333
  • NumNodesOfType_Active_PREBXBY=8348
  • NumNodesOfType_Active_VFULLHEX=2183
  • NumNodesOfType_Active_VLONG=762
  • NumNodesOfType_Active_VUNIHEX=2461
  • NumNodesOfType_Gnd_DOUBLE=12
  • NumNodesOfType_Gnd_DUMMY=1
  • NumNodesOfType_Gnd_INPUT=66
  • NumNodesOfType_Gnd_OMUX=56
  • NumNodesOfType_Gnd_OUTPUT=60
  • NumNodesOfType_Gnd_PREBXBY=65
  • NumNodesOfType_Vcc_CNTRLPIN=24
  • NumNodesOfType_Vcc_DUMMY=3
  • NumNodesOfType_Vcc_INPUT=164
  • NumNodesOfType_Vcc_PREBXBY=161
  • NumNodesOfType_Vcc_VCCOUT=157
 SiteStatistics
  • IBUF-DIFFM=4
  • IBUF-DIFFMI=2
  • IBUF-DIFFS=8
  • IBUF-DIFFSI=1
  • IBUF-IOB=3
  • IOB-DIFFM=9
  • IOB-DIFFS=9
  • SLICEL-SLICEM=3605
 		SiteSummary
  • BUFGMUX=24
  • BUFGMUX_GCLKMUX=24
  • BUFGMUX_GCLK_BUFFER=24
  • DIFFM=67
  • DIFFM_IFD_DELAY=5
  • DIFFM_IFF1=5
  • DIFFM_IFF2=4
  • DIFFM_INBUF=50
  • DIFFM_OFF1=1
  • DIFFM_OUTBUF=17
  • DIFFM_PAD=67
  • DIFFS=67
  • DIFFS_DIFFO_IN_USED=17
  • DIFFS_OUTBUF=17
  • DIFFS_PAD=67
  • DIFFS_PADOUT_USED=50
  • IBUF=19
  • IBUF_INBUF=19
  • IBUF_PAD=19
  • IOB=20
  • IOB_OUTBUF=20
  • IOB_PAD=20
  • SLICEL=7418
  • SLICEL_C1VDD=216
  • SLICEL_C2VDD=185
  • SLICEL_CYMUXF=1497
  • SLICEL_CYMUXG=1385
  • SLICEL_F=3077
  • SLICEL_F5MUX=323
  • SLICEL_FFX=3053
  • SLICEL_FFY=6563
  • SLICEL_G=5887
  • SLICEL_GNDF=761
  • SLICEL_GNDG=713
  • SLICEL_VDDF=3
  • SLICEL_XORF=1295
  • SLICEL_XORG=1304
  • SLICEM=1
  • SLICEM_F=1
  • SLICEM_FFX=1
  • SLICEM_G=1
  • SLICEM_GMC15_BLACKBOX=1
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:24] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:24]
  • S=[S_INV:24] [S:0]
 DIFFM
  • ICLK1=[ICLK1_INV:0] [ICLK1:5]
  • ICLK2=[ICLK2_INV:0] [ICLK2:4]
  • O1=[O1_INV:5] [O1:12]
  • OCE=[OCE:1] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:1]
 DIFFM_IFF1
  • CK=[CK:5] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:5]
  • LATCH_OR_FF=[FF:5]
 DIFFM_IFF2
  • CK=[CK:4] [CK_INV:0]
  • IFF2_INIT_ATTR=[INIT0:4]
  • LATCH_OR_FF=[FF:4]
 DIFFM_INBUF
  • IFD_DELAY_VALUE=[DLY3:5]
 DIFFM_OFF1
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:0] [D_INV:1]
  • LATCH_OR_FF=[FF:1]
  • OFF1_INIT_ATTR=[INIT0:1]
 DIFFM_OUTBUF
  • IN=[IN_INV:4] [IN:13]
 DIFFM_PAD
  • DIFF_TERM=[TRUE:50]
  • IOATTRBOX=[LVDS_25:67]
 DIFFS_PAD
  • DIFF_TERM=[TRUE:50]
  • IOATTRBOX=[LVDS_25:67]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:19]
  • PULL=[PULLUP:10]
 IOB
  • O1=[O1_INV:0] [O1:20]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:20]
 IOB_PAD
  • DRIVEATTRBOX=[12:20]
  • IOATTRBOX=[LVCMOS25:20]
  • SLEW=[SLOW:20]
 SLICEL
  • BX=[BX_INV:12] [BX:1753]
  • BY=[BY:2237] [BY_INV:39]
  • CE=[CE:5638] [CE_INV:83]
  • CIN=[CIN_INV:0] [CIN:1365]
  • CLK=[CLK:6128] [CLK_INV:673]
  • SR=[SR:1046] [SR_INV:62]
 SLICEL_CYMUXF
  • 0=[0:1494] [0_INV:0]
  • 1=[1_INV:4] [1:1493]
 SLICEL_CYMUXG
  • 0=[0:1385] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:323] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:2237] [CE_INV:77]
  • CK=[CK:2607] [CK_INV:446]
  • D=[D:3045] [D_INV:8]
  • FFX_INIT_ATTR=[INIT0:3018] [INIT1:35]
  • FFX_SR_ATTR=[SRLOW:3016] [SRHIGH:37]
  • LATCH_OR_FF=[FF:3053]
  • REV=[REV_INV:2] [REV:0]
  • SR=[SR:539] [SR_INV:34]
  • SYNC_ATTR=[ASYNC:2572] [SYNC:481]
 SLICEL_FFY
  • CE=[CE:5479] [CE_INV:76]
  • CK=[CK:5890] [CK_INV:673]
  • D=[D:6526] [D_INV:37]
  • FFY_INIT_ATTR=[INIT0:6495] [INIT1:68]
  • FFY_SR_ATTR=[SRLOW:6495] [SRHIGH:68]
  • LATCH_OR_FF=[FF:6563]
  • REV=[REV_INV:0] [REV:4]
  • SR=[SR:1010] [SR_INV:61]
  • SYNC_ATTR=[ASYNC:5690] [SYNC:873]
 SLICEL_XORF
  • 1=[1_INV:4] [1:1291]
 SLICEM
  • BY=[BY:1] [BY_INV:0]
  • CE=[CE:1] [CE_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
 SLICEM_F
  • DI=[DI:1] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
 SLICEM_FFX
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1]
  • FFX_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
 SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
 SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:1]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=24
  • O=24
  • S=24
 BUFGMUX_GCLKMUX
  • I0=24
  • OUT=24
  • S=24
 BUFGMUX_GCLK_BUFFER
  • IN=24
  • OUT=24
 DIFFM
  • DIFFI_IN=50
  • DIFFO_OUT=17
  • I=49
  • ICLK1=5
  • ICLK2=4
  • IQ1=5
  • IQ2=4
  • O1=17
  • OCE=1
  • OTCLK1=1
  • PAD=67
 DIFFM_IFD_DELAY
  • IN=5
  • OUT=5
 DIFFM_IFF1
  • CK=5
  • D=5
  • Q=5
 DIFFM_IFF2
  • CK=4
  • D=4
  • Q=4
 DIFFM_INBUF
  • DIFFI_IN=50
  • OUT=50
  • PAD=50
 DIFFM_OFF1
  • CE=1
  • CK=1
  • D=1
  • Q=1
 DIFFM_OUTBUF
  • IN=17
  • OUTN=17
  • OUTP=17
 DIFFM_PAD
  • PAD=67
 DIFFS
  • DIFFO_IN=17
  • PAD=67
  • PADOUT=50
 DIFFS_DIFFO_IN_USED
  • 0=17
  • OUT=17
 DIFFS_OUTBUF
  • DIFFO_IN=17
  • OUTP=17
 DIFFS_PAD
  • PAD=67
 DIFFS_PADOUT_USED
  • 0=50
  • OUT=50
 IBUF
  • I=19
  • PAD=19
 IBUF_INBUF
  • IN=19
  • OUT=19
 IBUF_PAD
  • PAD=19
 IOB
  • O1=20
  • PAD=20
 IOB_OUTBUF
  • IN=20
  • OUT=20
 IOB_PAD
  • PAD=20
 SLICEL
  • BX=1765
  • BY=2276
  • CE=5721
  • CIN=1365
  • CLK=6801
  • COUT=1385
  • F1=3074
  • F2=2227
  • F3=1235
  • F4=283
  • G1=5883
  • G2=5008
  • G3=2854
  • G4=683
  • SR=1108
  • X=1121
  • XB=16
  • XQ=3053
  • Y=1095
  • YQ=6563
 SLICEL_C1VDD
  • 1=216
 SLICEL_C2VDD
  • 1=185
 SLICEL_CYMUXF
  • 0=1494
  • 1=1497
  • OUT=1497
  • S0=1497
 SLICEL_CYMUXG
  • 0=1385
  • 1=1385
  • OUT=1385
  • S0=1385
 SLICEL_F
  • A1=3029
  • A2=2227
  • A3=1235
  • A4=283
  • D=3077
 SLICEL_F5MUX
  • F=323
  • G=323
  • OUT=323
  • S0=323
 SLICEL_FFX
  • CE=2314
  • CK=3053
  • D=3053
  • Q=3053
  • REV=2
  • SR=573
 SLICEL_FFY
  • CE=5555
  • CK=6563
  • D=6563
  • Q=6563
  • REV=4
  • SR=1071
 SLICEL_G
  • A1=5838
  • A2=5008
  • A3=2854
  • A4=683
  • D=5887
 SLICEL_GNDF
  • 0=761
 SLICEL_GNDG
  • 0=713
 SLICEL_VDDF
  • 1=3
 SLICEL_XORF
  • 0=1295
  • 1=1295
  • O=1295
 SLICEL_XORG
  • 0=1304
  • 1=1304
  • O=1304
 SLICEM
  • BY=1
  • CE=1
  • CLK=1
  • F1=1
  • F2=1
  • F3=1
  • F4=1
  • SR=1
  • XQ=1
 SLICEM_F
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
 SLICEM_FFX
  • CE=1
  • CK=1
  • D=1
  • Q=1
 SLICEM_G
  • DI=1
  • WS=1
 SLICEM_GMC15_BLACKBOX
  • MC15=1
  • WS2=1
 SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSF=1
  • WSG=1
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
Bitgen 54 54 0 0 0 0 0
CpldFit 66 66 0 0 0 0 0
MAP 27 27 0 0 0 0 0
NGDBuild 110 110 0 0 0 0 0
PAR 27 27 0 0 0 0 0
_impact 82 82 0 0 0 0 0
edif2ngd 1798 1798 0 0 0 0 0
hprep6 53 53 0 0 0 0 0
trce 29 29 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 94 94 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=55 NGDBUILD_NUM_BUFG=23 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=1322
NGDBUILD_NUM_FDC=5 NGDBUILD_NUM_FDCE=224 NGDBUILD_NUM_FDC_1=2 NGDBUILD_NUM_FDE=6581
NGDBUILD_NUM_FDPE=78 NGDBUILD_NUM_FDR=125 NGDBUILD_NUM_FDRE=933 NGDBUILD_NUM_FDRS=6
NGDBUILD_NUM_FDR_1=56 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_FDSE=25 NGDBUILD_NUM_FD_1=8
NGDBUILD_NUM_GND=41 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_IBUFDS=47 NGDBUILD_NUM_IBUFGDS=3
NGDBUILD_NUM_INV=725 NGDBUILD_NUM_LUT1=937 NGDBUILD_NUM_LUT2=3067 NGDBUILD_NUM_LUT3=3139
NGDBUILD_NUM_LUT4=851 NGDBUILD_NUM_MUXCY=2658 NGDBUILD_NUM_MUXF5=321 NGDBUILD_NUM_OBUF=20
NGDBUILD_NUM_OBUFDS=17 NGDBUILD_NUM_SRLC16E=2 NGDBUILD_NUM_VCC=43 NGDBUILD_NUM_XORCY=2413
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=55 NGDBUILD_NUM_BUFG=24 NGDBUILD_NUM_FD=1339 NGDBUILD_NUM_FDC=37
NGDBUILD_NUM_FDCE=228 NGDBUILD_NUM_FDC_1=2 NGDBUILD_NUM_FDE=6584 NGDBUILD_NUM_FDPE=78
NGDBUILD_NUM_FDR=141 NGDBUILD_NUM_FDRE=1125 NGDBUILD_NUM_FDRS=6 NGDBUILD_NUM_FDR_1=56
NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_FDSE=25 NGDBUILD_NUM_FD_1=8 NGDBUILD_NUM_GND=50
NGDBUILD_NUM_IBUF=18 NGDBUILD_NUM_IBUFDS=47 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_IBUFGDS=3
NGDBUILD_NUM_INV=733 NGDBUILD_NUM_LUT1=1106 NGDBUILD_NUM_LUT1_L=7 NGDBUILD_NUM_LUT2=3117
NGDBUILD_NUM_LUT2_L=18 NGDBUILD_NUM_LUT3=3149 NGDBUILD_NUM_LUT3_L=23 NGDBUILD_NUM_LUT4=922
NGDBUILD_NUM_LUT4_L=39 NGDBUILD_NUM_MUXCY=2663 NGDBUILD_NUM_MUXCY_L=219 NGDBUILD_NUM_MUXF5=324
NGDBUILD_NUM_OBUF=20 NGDBUILD_NUM_OBUFDS=17 NGDBUILD_NUM_PULLUP=10 NGDBUILD_NUM_SRLC16E=2
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=50 NGDBUILD_NUM_XORCY=2598
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=Mixed -ofn=<design_top> -ofmt=NGC
-top=<design_top> -lso=FPGARFCounterComprator.lso -p=XC3S1600E-4FG320 -uc=FPGARFCounterComprator.XCF
-vlgincdir={C:\Users\Daniel\DOCUME~1\Protel\Timing\ALTIUM~1\Software\FPGA-V~1\RFCOUN~1\PROJEC~2\Spartan3\ C:\Users\Daniel\DOCUME~1\Protel\Timing\ALTIUM~1\Software\FPGA-V~1\RFCOUN~1\} -define={} -iobuf=Yes -fsm_encoding=Auto
-resource_sharing=Yes -fsm_extract=Yes -max_fanout=100 -opt_mode=Area
-opt_level=2 -keep_hierarchy=Yes -iob=Auto -register_duplication=Yes
-rtlview=No