Altium

Design Rule Verification Report

Date:		8/9/2024
Time:		2:30:58 PM
Elapsed Time:		00:00:02
Filename:		C:\Users\daniel.sigg\Documents\Protel\EtherCAT\Concentrator\ConcentratorWhitening\ConcentratorWhitening.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=12mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=12mil) (Max=50mil) (Preferred=12mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=9.8mil) (All)	0
Hole Size Constraint (Min=15mil) (Max=250mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)	0
Silk To Solder Mask (Clearance=6mil) (IsPad),(All)	0
Silk to Silk (Clearance=10mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0