# Design Rule Verification Report

Date: |  | 1/12/2026
Time: |  | 11:49:33 AM
Elapsed Time: |  | 00:00:00
Filename: |  | C:\Users\daniel.sigg\Documents\Protel\Converter\FastDigitalServo\TimingClock\TimingClock.PcbDoc
Warnings: |  | 0
Rule Violations: |  | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=8mil) (All),(All) | 0
Clearance Constraint (Gap=8mil) (InDifferentialPair('VCOCLK') or InDifferentialPair('OSCCLK') or InDifferentialPair('EXTCLK') or InDifferentialPair('IN1')),(InDifferentialPair('VCOCLK') or InDifferentialPair('OSCCLK') or InDifferentialPair('EXTCLK') or InDifferentialPair('IN1')) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Modified Polygon (Allow modified: No), (Allow shelved: No) | 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) | 0
Routing Topology Rule(Topology=Shortest) (All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Minimum Annular Ring (Minimum=5mil) (All) | 0
Hole Size Constraint (Min=8mil) (Max=100mil) (All) | 0
Hole To Hole Clearance (Gap=10mil) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) | 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) | 0
Silk to Silk (Clearance=10mil) (All),(All) | 0
Net Antennae (Tolerance=0mil) (All) | 0
Matched Lengths(Tolerance=5mil) (All) | 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) | 0
Total | 0