ECR: Upgrade existing DAQ front-end chassis with new PCIe timing boards

Document #:

LIGO-E2000625-v2

Document type:

E - Engineering documents

Abstract:

As part of A+ we developed a new timing interface that directly plugs into an PCI Express slot. This solution is fully compatible with the existing LIGO timing distribution system. It has the ability to support multiple sampling rates within the same chassis and is required to support the new 524kHz sampling ADCs for the filter cavity design.

Files in Document:

• PDF format (E2000625-v2.pdf, 208.0 kB)

Other Files:

• Microsoft Word form (E2000625-v2.docm, 32.9 kB)

Topics:

• Data Acquisition System

Authors:

• Daniel Sigg
• Marc Pirello
• Keith Thorne

Keywords:

ECR

Notes and Changes:

associated FRS ticket:
https://services.ligo-la.caltech.edu/FRS/show_bug.cgi?id=16594
V2 has Updated amounts, cost estimates, source of funding