Chassis Timing Interface
- Document #:
- LIGO-D070071-v1
- Document type:
- D - Drawings
Other Versions:
| LIGO-D070071-x0
06 Nov 2009, 11:56 |
- Abstract:
- Timing Slave FPGA board
- Files in Document:
-
- D070071-B.pdf (107.9 kB)
- D070071-C.pdf (106.4 kB)
- Other Files:
- D070071-A.pdf (110.5 kB)
- D070071-A.zip (1.3 MB)
- D070071-B.zip (2.1 MB)
- D070071-C.zip (3.9 MB)
- ICS/JIRA Record:
-
- ICS_LINK
- Topics:
- Authors:
- Notes and Changes:
- This is revision C.
//Revision A and B added.
- Related Documents:
- Referenced by:
- LIGO-E0900016-v1: Integration Plan Slave Module Advanced LIGO
- LIGO-D0900301-v1: Timing IRIG-B
- LIGO-E090001-v1: Chassis Integration Plan Clock, Gate, and DuoTone Signal Interface Advanced LIGO
- LIGO-D1001715-v3: aLIGO, DAS, IO EXPANSION CHASSIS, MECHANICAL ASSY
- LIGO-E090003-v1: Timing System Document Map Advanced LIGO