aLIGO SUS ITM and BS System Wiring Diagrams (for H1/L1)

Document #:

LIGO-D1100022-v13

Document type:

D - Drawings

Abstract:

aLIGO SUS ITM and BS Wiring Diagrams for H1 and L1.

REDLINES
-v13 1. Page 2: ITMY PUM Driver should be a D1100303 PUM Driver chassis, not a UIM D0902668 chassis. (ITMX on Page 4 is correct).

-v13 2. Page 9: SUS-R5 is for ITMX, but ESD driver and satamps are labeled "ITMY"

-v13 3. Page 9: Labels for Optical Lever assignment to whitening chassis is flipped from reality; ITMY and BS oplevs go into SUS-R6 whitening chassis, and ITMX goes into SUS-R5 whitening chassis (chassis location is correct on Page 6).

-v13 7. Page 7: DAC Card name and IO chassis card slot are incompatible with where ADC cards are (both ADC0+ADC1 and DAC0+DAC1 cards are labeled to be in the same IOC Card Slot 1 and 3), and inconsistent with as-built slot assignment (D1301004, D1400014). At least DAC0+DAC1 should be in IOC slot 2 and 4, but then the assignment of which DACs go into IOC slots 5 through 10 are confusing.
True map (as of ECR E2200324) is:
DAC0 = Card 2 = ITMY M0 F1F2F3SD, ITMY M0RTSD/R0RTSD
DAC1 = Card 4 = ITMY R0 F1F2F3SD, ITMX R0 F1F2F3SD

DAC2 = Card 5 = ITMY PUM ULLLURLR, BS MID ULLLURLR
DAC3 = Card 6 = BS TOP F1F2F3LF, BS TOP RTSDxxxx

DAC4 = Card 7 = ITMX M0 F1F2F3SD, ITMX M0RTSD/R0RTSD
DAC5 = Card 8 = ITMY UIM ULLLURLR, ITMX UIM ULLLURLR

DAC6 = Card 9 = ITMX TST PI ULLLURLR, ITMY TST PI ULLLURLR
DAC7 = Card 10 = ITMX TST BSCM, ITMY TST BSCM, ITMX PUM ULLLURLR

-v13 4. Page 8: SUSAUXB123 IO chassis lives in SUS-C5 as listed under the ADC cards, but in U-height 14 (as shown on pg 14). Monitor ADCs 0 thru 6 errantly list IO chassis U-height as Slot 24 (a copy and paste error from the "control" IO chassis SUSB123).

-v13 5. SUSAUXB123 coil driver monitor AA chassis component C80 (for BS TOP F1F2F3LF NOISEMON, BS TOP RT SDxxxx NOISEMON, BS TOP F1F2F3LF SFVMON, ITMY M0 LFRT/R0 LFRT SFVMON) is in SUS-C6 U-height U12 not U14 (correctly shown on page 10).

-v13 6. Altium detail: Change ESD library part to be ITM_ESD. Currently it was incorrectly labeled/designated as ETM_ESD in SUS_Library

Files in Document:

• PDF File (D1100022_v13_Wiring ITM_BS_ESD.pdf, 1.4 MB)

Other Files:

• Altium Files (D1100022-v13_Altium_Files_.zip, 230.4 kB)
• Cable List (D1100022_v13_Wiring ITM_BS_CableList.xlsx, 35.0 kB)

ICS/JIRA Record:

• d1100022

Topics:

• Suspensions

Authors:

• Jay Heefner
• Mohana Mageswaran

Keywords:

H1 L1 ITM BS System Wiring Diagram aLIGO Schematic

Notes and Changes:

Major overhaul from -v12.
- Upgraded wiring layout to modern format as has been done for HAM56 D1002740 and HAM7 D2000202.
- Folded in various other drawings
- ITM ESD Wiring Diagram D1500464
- SUS Hardware Watchdog (Never drawn officially)
- For the first time,
- Defined U heights for field racks SUS-R5 and SUS-R6 (IIET 5097 https://services1.ligo-la.caltech.edu/FRS/show_bug.cgi?id=5097)
- Defined locations of ADC / DAC / BIO cards in IO chassis (Usually reserved for Local CDS software / IO chassis teams to figure out a la D1301004 and D1400014.)

Related Documents:

Referenced by:

• LIGO-T1000286-v9: aLIGO Quadruple Suspension (QUAD) Final Design Document