IO Interface Backplane (LVDS)
- Document #:
- LIGO-D2000297-v2
- Document type:
- D - Drawings
Other Versions:
| LIGO-D2000297-v1
24 Feb 2021, 09:26 |
- Abstract:
- This is a new IO backplane that will interface the PCIe timing board. It uses LVDS lines on a DB37 connector to provide clock signals to individual slots.
- Files in Document:
-
- D2000297-v2.pdf (5.6 MB)
- Other Files:
- D2000297-v2-assembly.zip (356.1 kB)
- D2000297-v2-pinout.pdf (125.0 kB)
- D2000297-v2.zip (6.1 MB)
- ICS/JIRA Record:
-
- ICS_LINK
- Topics:
- Authors:
- Notes and Changes:
- Reverse slot numbering
Prior Revision of Backplane
https://dcc.ligo.org/LIGO-D1500101
- Related Documents:
- LIGO-D2100184: Backplane Test Adapter
- Referenced by:
- LIGO-D1500101-v3: Rear panel for power input to the IO Chassis
- LIGO-D1900002-v1: aLIGO, DAS, IO EXPANSION CHASSIS, MECHANICAL ASSY, W SPACERS
- LIGO-E2000328: PCIe Timing Interface