LIGO Document T1900639-v1

PCIe Implementation of Timing Interface System

Document #:
LIGO-T1900639-v1
Document type:
T - Technical notes
Other Versions:
Abstract:
PCIe Implementation of Timing Interface System.
Authors:
Keywords:
timing slave pcie
Notes and Changes:
https://adnacom.com/doc/Adnaco-R1BP1B-DWG.pdf (adnaco backplane)

Moving to the ARTIX 7 Xilinx Chips for better PCIe integration.

I am considering what system configurations this board is implemented in, and I want to be certain that it can continue to work in these applications.

* Timing Slave - Basis for all of this, I have fit this the PCIE board layout so far.
https://dcc.ligo.org/DocDB/0007/D070071/001/D070071-C.pdf

* Duotone Board & Adapter - This is straight forward and should be simple enough to implement on the timing board.
https://dcc.ligo.org/LIGO-E090001
https://dcc.ligo.org/DocDB/0012/D080335/001/D080335-B.pdf
https://dcc.ligo.org/DocDB/0005/D0902184/002/D0902184-v2.pdf

* 1PPS Locking - Again should be simple enough.
https://dcc.ligo.org/LIGO-E1200110
https://dcc.ligo.org/DocDB/0001/D080702/002/D080702-B.pdf
https://dcc.ligo.org/DocDB/0004/D080665/001/D080665-B.pdf

* IRIG-B
https://dcc.ligo.org/LIGO-D0900301
https://dcc.ligo.org/DocDB/0000/D0900301/001/D0900301-A.pdf
https://dcc.ligo.org/DocDB/0000/D0900304/001/D0900304-A.pdf
https://dcc.ligo.org/DocDB/0000/D0900305/001/D0900305-A.pdf

* RF Source

* Timing Slave

* Timing Master

* Backplane
https://dcc.ligo.org/LIGO-D0902029

* New Backplane LVDS
https://dcc.ligo.org/LIGO-D2000297

* ADL General Standards DAC
https://dcc.ligo.org/LIGO-D0902496

* ADL General Standards ADC
https://dcc.ligo.org/DocDB/0005/D0902006/001/D0902006-v1.pdf

* Contec Cards
DIO-1616L-PE
DIO-6464L-PE

Referenced by:

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