LIGO Document D1400301-v10
- A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.
- Version 10 Notes
Changed order of quadrant selector and high-pass filter to eliminate two stages. Changed quadrant selector to relay based solution to accommodate higher voltages. Updated pole-zero frequency from 40Hz zero to 50Hz zero to accurately reflect the as-built schematic.
- held from 28 Oct 2014 to 29 Oct 2014 in LHO/OSB front room
DCC Version 3.4.0, contact
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