ESD Low Voltage Driver Block Diagram

Document #:

LIGO-D1400301-v10

Document type:

D - Drawings

Abstract:

A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.

Files in Document:

• PDF Version (NewESD_v10.pdf, 80.2 kB)

Other Files:

• Visio Version (NewESD_v10.vsd, 266.5 kB)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Sensing and Control

Authors:

• Rich Abbott
• Peter Fritschel
• Carl Adams

Keywords:

ESD

Notes and Changes:

Version 10 Notes
Changed order of quadrant selector and high-pass filter to eliminate two stages. Changed quadrant selector to relay based solution to accommodate higher voltages. Updated pole-zero frequency from 40Hz zero to 50Hz zero to accurately reflect the as-built schematic.

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