LIGO Document D1400301-v14
- A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.
- Version 14 incorporates revisions to the ITM ESD block diagram
as recorded during the March 2016 LVC Meeting
- held from 28 Oct 2014 to 29 Oct 2014 in LHO/OSB front room
DCC Version 3.4.0, contact
Document Database Administrators